1. Field of the Invention
The present invention relates to a large scale integration (LSI) system including a plurality of LSI circuit chips mounted on a board. More particularly, it relates to an LSI system adapted to measuring a voltage appearing at each pin of the chips using a non-contact approach to test the LSI system.
Note, in the following description, the term "LSI" indicates a semiconductor chip including a plurality of LSI circuits and a package accommodating the chip, as long as a specific definition is not added thereto. Also, a voltage appearing at each pin of the LSI is hereinafter referred to as an LSI pin voltage.
2. Description of the Related Art
A test of an LSI system is classified into a function test and a net test. The function test is carried out by applying input signals via a conductor on a board to LSIs mounted on the board and examining whether or not expected values corresponding to the input signals are obtained from output terminals of each LSI. On the other hand, the net test is carried out by measuring voltages appearing on wiring connecting input/output terminals (pins) between each LSI and examining whether or not each voltage drop corresponding to the measured voltages is within a permissible range. In any case, the test of the LSI system is carried out by detecting LSI pin voltages. Namely, in the function test, a judgement of logic "1" or "0" is made in accordance with whether or not the LSI pin voltage is higher than a certain reference voltage, and a judgement is further made of whether or not this logic coincides with the expected value. On the other hand, in the net test, the value of the voltage drop is obtained by measuring voltages at both ends of the wiring connecting input/output pins between each LSI and detecting a voltage difference therebetween.
For example, assuming that a voltage of -0.9 V indicates "1" and a voltage of -1.7 V indicates "0", a voltage of -1.3 V is selected as the reference voltage in the function test. On the other hand, in the net test, a judgement is made of whether or not the voltage of -0.9 V is finally lowered to a voltage of -1.1 V. Namely, the net test is carried out with a margin of 200 mV on the "H" level side. Accordingly, for example, an advantage is gained in that it is possible to exclude an LSI system in which the voltage level fluctuates around a voltage of -1.3 V due to noise inevitably occurring in real operation and in which an erroneous operation may be carried out, although the LSI system is considered to be "good" at a voltage higher than -1.3 V in the function test.
Namely, to reliably carry out such a net test, the LSI pin voltage must be accurately detected. In connection with this, the reference voltage must be stably fed to each LSI with a constant and equal value. In a known technique, however, an LSI system satisfactorily meeting these requirements has not been proposed.